Basic understanding of Jtag, boundary scan, P1500, design for debug, SMS, scan, Tessent edt compression logic, SSN, hierarchical scan (INTEST/EXTEST), clock gating, power gating, ISO control Understanding of PD floorplan, scan/DFX repeaters, clock/reset structure, DFX for DDR/PHY/PCIE, FUSE, source synchronous bus With the above knowledges and design bounding box, create